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ML145442 ML145443
Single-Chip 300-Baud Modem
Legacy Device: Motorola MC145442B, MC145443B
The ML145442 and ML145443 silicon-gate CMOS single-chip low-speed modems contain a complete frequency shift keying (FSK) modulator, demodulator, and filter. These devices are compatible with CCITT V (ML145442) .21 and Bell 103 (ML145443) specifications. Both devices provide full-duplex or half-duplex 300-baud data communication over a pair of telephone lines. They also include a carrier detect circuit for the demodulator section and a duplexer circuit for direct operation on a telephone line through a simple transformer. This Device Offers The Following Performance Features: * * * * * * * * * * * * * * * * ML145442 Compatible with CCITT V .21 ML145443 Compatible with Bell 103 Low-Band and High-Band Band-Pass Filters On-Chip Simplex, Half-Duplex, and Full-Duplex Operation Originate and Answer Mode Analog Loopback Configuration for Self Test Hybrid Network Function On-Chip Carrier Detect Circuit On-Chip Adjustable Transmit Level and CD Delay Timing On-Chip Crystal Oscillator (3.579 MHz) Single +5 V Power Supply Operation Internal Mid-Supply Generator Power-Down Mode Pin Compatible with MM74HC943 Capable of Driving -9 dBm into a 600 W Load Operating Temperature Range = TA -40 to +85C
P DIP 20 = RP PLASTIC DIP CASE 738
20 1
20 1
SOG 20 = -6P SOG PACKAGE CASE 751D
CROSS REFERENCE/ORDERING INFORMATION LANSDALE MOTOROLA PACKAGE P DIP 20 H SO 20W P DIP 20 H SO 20W MC145442BP MC145442BDW MC145443BP MC145443BDW ML145442RP ML145442-6P ML145443RP ML145443-6P
Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.
PIN ASSIGNMENT
DSI LB CD CDT RxD V DD CDA X out X in FB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 TLA VAG Exl TxA RxA1 RxA2 SQT MODE V SS TxD
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BLOCK DIAGRAM 4 7 CARRIER 3 DETECT AC AMP * DEMOD 5 CDT CDA CD RxD
RxA2 15 RxA1 16
LOW-BAND BPF
- +
AAF
S/H
HIGH-BAND BPF
10 FB 1 DSI SMOOTHING FILTER - + 17 18 TxA ExI
LB MODE SQT TxD TLA Xout Xin
2 13 14 11 20 8 9
MODE CONTROL MODULATOR OSCILLATOR CLOCK DIVIDER SAMPLING CLOCK: 77.82 kHz SAMPLING CLOCK: 19.46 kHz
INTERNAL VAG
ANALOG GROUND GENERATOR
19 6 12
VAG VDD VSS
* Refer to the FB pin description.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating Supply Voltage DC Input Voltage DC Output Voltage Clamp Diode Current, per Pin DC Output Current, per Pin Power Dissipation Operating Temperature Range Storage Temperature Range Symbol VDD Vin Vout IIK, IOK Iout PD TA Tstg Value -0.5 to 7.0 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 20 28 500 -40 to 85 -65 to 150 Unit V V V mA mA mW C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage DC Input or Output Voltage Input Rise or Fall Time Crystal Frequency* Symbol VDD Vin, Vout tr, tf fcrystal Min 4.5 0 -- 3.2 Max 5.5 VDD 500 5.0 Unit V V ns MHz
* Changing the crystal frequency from 3.579 MHz will change the output frequencies. The change in output frequency will be proportional to the change in crystal frequency.
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ML145442, ML145443
DC ELECTRICAL CHARACTERISTICS (VDD = 5.0 V 10%, TA = -40 to 85C)
Characteristic High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage IOH = 20 A IOH = 2 mA IOH = 20 A Low-Level Output Voltage IOL = 20 A IOL = 2 mA IOL = 20 A Input Current LB Xin, TxD, Mode, SQT LB Xin, TxD, Mode, SQT CD, RxD CD, RxD Xout VOL CD, RxD CD, RxD Xout LB, TxD, Mode, SQT RxA1, RxA2 (0 TA 85C) RxA1, RxA2 (-40 TA < 0C) Xin Iin -- -- -- -- -- -- -- -- -- Xin All Other Inputs Cin VAG VCDA Rf -- -- 2.4 1.1 10 -- -- 0.05 -- 10 -- -- 7 200 10 -- 2.5 1.2 20 0.1 0.4 -- 1.0 12 20 10 10 300 -- 10 2.6 1.3 30 A Symbol VIH VIL VOH VDD - 0.1 3.7 -- -- -- VDD - 0.05 -- -- -- V Min VDD - 0.8 3.15 -- -- Typ -- -- -- -- Max -- -- 0.8 1.1 Unit V V V
Quiesent Supply Current (Xin or fcrystal = 3.579 MHz) Power-Down Supply Current Input Capacitance VAG Output Voltage (IO = 10 A) CDA Output Voltage (IO = 10 A) Line Driver Feedback Resistor
IDD
mA A pF V V k
AC ELECTRICAL CHARACTERISTICS
(VDD = 5.0 V 10%, TA = -40 to 85C, Crystal Frequency = 3.579 MHz 0.1%; See Figure 1) Characteristic TRANSMITTER Power Output on TxA RL = 1.2 k, RTLA = RL = 1.2 k, RTLA = 5.5 k Second Harmonic Power RL = 1.2 k RECEIVE FILTER AND HYBRID Hybrid Input Impedance RxA1, RxA2 FB Output Impedance Adjacent Channel Rejection DEMODULATOR Receive Carrier Amplitude Dynamic Range Bit Jitter (S/N = 30 dB, Input = -38 dBm, Bit Rate = 300 baud) Bit Bias Carrier Detect Threshold (CDA = 1.2 V or CDA grounded through a 0.1 F capacitor) On to Off Off to On -48 -- -- -- -- -- -- 36 100 5 -44 -47 -12 -- -- -- -- -- dBm dB s % dBm 40 -- -48 50 16 -- -- -- -- k k dBm dBm -13 -10 -- -12 -9 - 56 -11 -8 -- dBm Min Typ Max Unit
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LANSDALE Semiconductor, Inc.
Table 1. Bell 103 and CCITT V.21 Frequency Characteristics
Originate Mode 3.579 MHz 0.1% Data Transmit Receive Answer Mode Transmit Receive
Bell 103 (ML145443) 8 9 R TLA X out X in 11 20 TLA TxD V DD 17 TxA 15 RxA2 ML145442 600 ML145443 600 16 5 RxA1 RxD TEST CDT FB OUTPUT TEST 4 10 INPUT 0.1 F 0.1 F C CDT C FB T R A N S MIT C A R R IE R LE V E L ( dBm) 0 Space D in Mark 1070 Hz 1270 Hz 2025 Hz 2225 Hz 2025 Hz 2225 Hz 1070 Hz 1270 Hz
CCITT V.21 (ML145442) Space Mark D out 1180 Hz 980 Hz 1850 Hz 1650 Hz 1850 Hz 1650 Hz 1180 Hz 980 Hz
NOTE: Actual frequencies may be 5 Hz assuming 3.579545 MHz crystal is used. MAXIMUM LEVEL OF OUT-OF-BAND ENERGY RELATIVE TO THE TRANSMIT CARRIER LEVEL INTO 600 (kHz) 0 2 3.4 4 16 64 256
Figure 1. AC Characteristics Evaluation Circuit
PIN DESCRIPTIONS VDD Positive Power Supply (Pin 6) This pin is normally tied to 5.0 V . VSS Negative Power Supply (Pin 12) This pin is normally tied to 0 V . VAG Analog Ground (Pin 19) Analog ground is internally biased to (VDD - VSS)/2. This pin must be decoupled by a capacitor from VAG to VSS and a capacitor from VAG to VDD. Analog ground is the common bias line used in the switched capacitor filters, limiter, and slicer in the demodulation circuitry. TLA Transmit Level Adjust (Pin 20) This pin is used to adjust the transmit level. Transmit level adjustment range is typically from -12 dBm to -9 dBm. (See Legacy Applications Information.) TxD Transmit Data (Pin 11) Binary information is input to the transmit data pin. Data entered for transmission is modulated using FSK techniques. A logic high input level represents a mark and a logic low represents a space (see Table 1). TxA Transmit Carrier (Pin 17) This is the output of the line driver amplifier. The transmit carrier is the digitally synthesized sine wave output of the modulator derived from a crystal oscillator reference. When a 3.579 MHz crystal is used the frequency outputs shown in Table 1 apply. (See Legacy Applications Information.)
-20 -25 15 dB/OCTAVE
-55 -60
Figure 2. Out-of-Band Energy
ExI External Input (Pin 18) The external input is the non-inverting input to the line driver. It is provided to combine an auxiliary audio signal or speech signal to the phone line using the line driver. This pin should be connected to VAG if not used. The average level must be the same as VAG to maintain proper operation. (See Legacy Applications Information.) DSI Driver Summing Input (Pin 1) The driver summing input may be used to connect an external signal, such as a DTMF dialer, to the phone line. A series resistor, RDSI, is needed to define the voltage gain AV (see Legacy Applications Information and Figure 6). When applying a signal to the DSI pin, the modulator should be squelched by bringing SQT (pin 14) to a logic high level. The voltage gain, AV is cal, culated by the formula AV = -Rf/RDSI (where Rf 20 k). For example, a 20 k resistor for RDSI will provide unity gain (AV = -20 k/20 k = -1). This pin must be left open if not used. RxD Receive Data (Pin 6) The receive data output pin presents the digital binary data resulting from the demodulation of the receive carrier. If no carrier is present, CD high, the receive data output (RxD) is clamped high.
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RxA2, RxA1 Receive Carrier (Pins 15, 16) The receive carrier is the FSK input to the demodulator through the receive band-pass filter. RxA1 is the non-inverting input and RxA2 is the inverting input of the receive hybrid (duplexer) operational amplifier. LB Analog Loopback (Pin 2) When a high level is applied to this pin (SQT must be low), the analog loopback test is enabled. The analog loopback test connects the TxA pin to the RxA2 pin and the RxA1 to analog ground. In loopback, the demodulator frequencies are switched to the modulation frequencies for the selected mode. (See Tables 1 and 2 and Figures 4c and 4d.) When LB is connected to analog ground (VAG), the modulator generates an echo cancellation tone of 2100 Hz for ML145442 CCITT V and 2225 Hz for ML145443 Bell 103 systems. For .21 normal operation, this pin should be at a logic low level (VSS). The power-down mode is enabled when both LB and SQT are connected to a logic high level (see Table 2).
Table 2. Functional Table
MODE Pin 13 1 0 X X X X X SQT Pin 14 0 0 0 0 1 1 1 LB Pin 2 0 0 VAG (VDD/2) 1 0 VAG (VDD/2) 1 Operating Mode Originate Mode Answer Mode Echo Tone Analog Loopback Squelch Mode Squelch Mode Power Down
MODE Mode (Pin 13) This input selects the pair of transmit and frequencies used during modulation and demodulation. When a logic high level is placed on this input, originate (Bell) or channel 1(CCITT) is selected. When a low level is placed on this input, answer (Bell) or channel 2 (CCITT) is selected. (See Tables 1 and 2 and Figure 4.) CDT Carrier Detect Timing (Pin 4) A capacitor on this pin to VSS sets the amount of time the carrier must be present before CD goes low (see Legacy Applications Information for the capacitor values). CD Carrier Detect Output (Pin 3) This output is used to indicate when a carrier has been sensed by the carrier detect circuit. This output goes to a logic low level when a valid signal above the maximum threshold level (defined by CDA, pin 7) is maintained on the input to the hybrid circuit longer then the response (defined by CDT, pin 4). This pin is held at the logic low level until the signal falls below the maximum
threshold level for longer than the turn off time. (See Legacy Applications Information and Figure 5.) CDA Carrier Detect Adjust (Pin 7) An external voltage may be applied to this pin to adjust the carrier detect threshold. The threshold hysteresis is internally fixed at 3 dB (see Legacy Applications Information). Xout, Xin Crystal Oscillator (Pins 8, 9) A crystal reference oscillator is formed when a 3.579 MHz crystal is connected between these two pins. Xout (pin 8) is the output of the oscillator circuit, and Xin (pin 9) is the input to the oscillator circuit. When using an external clock, apply the clock to the Xin (pin 9) pin and leave Xout (pin 8) open. An internal 10 M resistor and internal capacitors, typically 10 pF on Xin and 16 pF on Xout, allow the crystal to be connected without any other external components. Printed circuit board layout should keep external stray capacitance to a minimum. FB Filter Bias (Pin 10) This is the negative input to the AC amplifier. In normal operation, this pin is connected to analog ground through a 0.1F bypass capacitor in order to cancel the input offset voltage of the limiter. It has a nominal input impedance of 16 k (see Figure 3). SQT Transmit Squelch (Pin 14) When this input pin is at a logic high level, the modulator is disabled. The line driver remains active if LB is at a logic low level (see Table 2). When both LB and SQT are connected to a logic high level (see Table 2), the entire chip is in a power down state and all circuitry except the crystal oscillator is disabled. Total power supply current decreases from 10 mA (max) to 300 A (max).
FROM BAND-PASS FILTER
+ -
TO CARRIER DETECT CIRCUIT AND DEMODULATOR
490 k 16 k 10 FB 0.1 F
Figure 3. AC Amplifier Circuit
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GENERAL DESCRIPTION The ML145442 and ML145443 are full-duplex low-speed modems. They provide a 300-baud FSK signal for bidirectional data transmission over the telephone network. They can be operated in one of four basic configurations as determined by the state of MODE (pin 13) and LB (pin 2).The normal (non-loopback) and self test (loopback) modes in both answer and originate modes will be discussed. For an originate or channel 1 mode, a logic high level is placed on MODE (pin 13) and a logic low level is placed on LB (pin 2). In this mode, transmit data is input on TxD, where it is converted to a FSK signal and routed through a low-band band-pass filter. The filtered output signal is then buffered by the Tx op-amp line driver, which is capable of driving -9 dBm onto a 600 line. The receive signal is connected through a hybrid duplexer circuit on pins 15 and 16, RxA2 and RxA1. The signal then passes through the anti-aliasing filter, the sample-and-hold circuit, is switched into the high-band band-pass filter, and then switched into the AC amplifier circuit. The output of the ac amplifier circuit is routed to the demodulator circuit and demodulated. The resulting digital data is then output through RxD (pin 5). The carrier detect circuit receives its signal from the output of the AC amplifier circuit and goes low when the incoming signal is detected (see Figure 4a).
In the answer or channel 2 mode, a logic low level is placed on MODE (pin 13) and on LB (pin 2). In this mode, the data follows the same path except the FSK signal is routed to the high-band band-pass filter and the sample-and-hold signal is routed through the low-band band-pass filter (see Figure 4b). In the analog loopback originate or channel 1 mode, a logic high level is placed on MODE (pin 13) and on LB (pin 2). This mode is used for a self check of the modulator, demodulator, and low-band pass-band filter circuit. The modulator side is configured exactly like the originate mode above except the line driver output (TxA, pin 17) is switched to the negative input of the hybrid op-amp. The RxA2 input pin is open in this mode and the non-inverting input of the hybrid circuit is connected to VAG. The sample-and-hold output bypasses the filter so that the demodulator receives the modulated Tx data (see Figure 4c). This test checks all internal device components except the high-band band-pass filter, which can be checked in the answer or channel 2 mode test. In the analog loopback or channel 2 mode, a logic low level is placed on MODE (pin 13) and a logic high level on LB (pin 2). This mode is used for a self check of the modulator, demodulator, and high-band pass-band filter circuit. This configuration is exactly like the originate loopback mode above, except the signal is routed through the high-band pass-band filter (see Figure 4d).
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15 - RxA1 16 + AAF S/H CARRIER DETECT
ML145442, ML145443
RxA2
3
CD
LOW-BAND BPF
AC AMP
DEMOD
5 1
RxD DSI
TxD
11
MODULATOR
HIGH-BAND BPF
SMOOTHING FILTER
- +
17
TxA
18
Exl
(a) Originate/Channel 1 Mode (MODE = High, LB = Low)
RxA2 15 - RxA1 16 + CARRIER DETECT 3 CD
AAF
S/H
LOW-BAND BPF
AC AMP
DEMOD
5 1
RxD DSI
TxD
11
MODULATOR
HIGH-BAND BPF
SMOOTHING FILTER
- +
17
TxA
18
(b) Answer/Channel 2 Mode (MODE = Low, LB = Low)
RxA2 15 - RxA1 16 + AAF S/H LOW-BAND BPF CARRIER DETECT
Exl
3
CD
AC AMP
DEMOD
5 1
RxD DSI
TxD
11
MODULATOR
HIGH-BAND BPF
SMOOTHING FILTER
- +
17
TxA Exl
18
(c) Originate/Channel 1 Mode and Analog Loopback State (MODE = High, LB = Low)
RxA2 15 - + CARRIER DETECT 3 CD
RxA1
16
AAF
S/H
LOW-BAND BPF
AC AMP
DEMOD
5 1
RxD DSI
TxD
11
MODULATOR
HIGH-BAND BPF
SMOOTHING FILTER
- +
17
TxA Exl
18
(d) Answer/Channel 2 Mode and Analog Loopback State (MODE = Low, LB = Low) Figure 4. Basic Operating Modes
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Legacy Applications Information
CARRIER DETECT TIMING ADJUSTMENT The value of a capacitor, CCDT at CDT (pin 4) determines how long a received modem signal must be present above the minimum threshold level before CD (pin 3) goes low. The CCDT capacitor also determines how long the CD pin stays low after the received modem signal goes below the mini mum threshold. The CD pin is used to distinguish a strong modem signal from random noise. The following equations show the relationship between tCDL, the time in seconds required for CD to go low; tCDH, the time in seconds required for CD to go high; and CCDT, the capacitor value in F. Valid signal to CD response time: tCDL 6.4 X CCDT Invalid signal to CD off time: tCDH 0.54 X CCDT Example: tCDL 6.4 X 0.1 F 0.64 seconds tCDH 0.54 X 0.1 F 0.054 seconds CARRIER DETECT THRESHOLD ADJUSTMENT The carrier detect threshold is set by internal resistors to activate CD with a typical -44 dBm (into 600 ) signal and deactivate CD with a typical -47 dBm signal applied to the input of the hybrid circuit. The carrier detect threshold level can be adjusted by applying an external voltage on CDA (pin 7). The following equations may be used to find the CDA voltage required for a given threshold voltage. (Von and Voff are in Vrms.) VCDA = 244 x Von VCDA = 345 x Voff Example (Internally Set) Von = 4.9 mV -44 dBm: VCDA = 244 x 4.9 mV = 1.2 V Voff = 3.5 mV -47 dBm: VCDA = 345 x 3.5 mV = 1.2 V Example (Externally Set) Von = 7.7 mV -40 dBm: VCDA = 244 x 7.7 mV = 1.9 V Voff = 5.4 mV -43 dBm: VCDA = 345 x 5.4 mV = 1.9 V The CDA pin has an approximate Thevenin equivalent voltage of 1.2 V and an output impedance of 100 k. When using the internal 1.2 V reference, a 0.1 F capacitor should be connected between this pin and VSS (see Figure 5). TRANSMIT LEVEL ADJUSTMENT The power output at TxA (pin 17) is determined by the value of resistor RTLA that is connected between TLA (pin 20) to VDD (pin 6). Table 3 shows the RTLA values and the corresponding power output for a 600 load. The voltage at TxA is twice the value of that at ring and tip because TxA feeds the signal through a 600 resistor RTx to a 600 line transformer (see Figure 7). When choosing resistor RTLA, keep in mind that -9 dBm is the maximum output level allowed from a modem onto the telephone line (in the U.S.). In addition, keep in mind that maximizing the power output from the modem optimizes the signal-to-noise ratio, improving accurate data transmission.
Table 3. Transmit Level Adjust
Output Transmit Level (Typical into 600 ) -12 dBm -11 dBm -10 dBm -9 dBm RTLA 19.8 k 9.2 k 5.5 k
THE LINE DRIVER The line driver is a power amplifier used for driving a telephone line. Both the inverting and noninverting input to the line driver are available for transmitting externally generated tones. Exl (pin 18) is the noninverting input to the line driver and gives a fixed gain of 2 (Ri = 50 k). The average signal level must be the same as VAG to maintain proper operation. This pin should be connected to VAG if not used. The driver summing input (DSI, pin 1) may be used to connect an external signal, such as a DTMF dialer, to the phone line. When applying a signal to the DSI pin, the modulator should be squelched by bringing SQT (pin 14) to a logic high level. DSI must be left open if not used.
AV = - Rf R DSI
In addition, the DSI pin is the inverting side of the line driver and allows adjustable gain with a series resistor RDSI (see Figure 6). The voltage gain, AV is determined by the equation: , where Rf 20 k. Example: A resistor value of 20 k for RDSI will provide unity gain. AV = - (20 k/20 k) = -1 .
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Legacy Applications Information
V DD HYBRID 16 RxA1 V ref CDA 7 V CDA 1.2 V THRESHOLD CONTROL SAMPLING CLOCK 4 CDT C CDT 0.1 F ac AMP AUTO-NULLED COMPARATOR 6 ms RETRIGGERABLE ONE-SHOT 3 CD
C CDA 0.1 F
Figure 5. Carrier Detect Circuit
MODULATOR OUTPUT R 0 = Rf R DSI DSI 1 ExI 18 VAG 19 Ri R0 Rf - + TxA 17
Figure 6. Line Driver Using the DSI Input
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LANSDALE Semiconductor, Inc.
Legacy Applications Information
L
ML145407
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Legacy Applications Information
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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